I'm Nobuho Hashimoto,
a graduate student
in the University of Tokyo
(Takamaeda Lab).

I'm researching on acceleration of
image and point-cloud processing on an FPGA.

(Natural / Programming) Languages

These are the languages I am using and have been used so far. But I am eager to try other languages and can become familiar with them soon based on my experience.

AtCoder: Cyan

Use on a Daily Basis

  • Japanese (Native)
  • Python
  • C / C++
  • Vitis / Vivado HLS
  • JavaScript
  • bash / zsh

Use Sometimes

  • English (Business)
  • HTML / CSS
  • PHP
  • System Verilog
  • OCaml

Have Used Before

  • Spanish
  • Thai
  • Chinese
  • MySQL / PostgreSQL
  • Ruby
  • Java
  • Scheme
  • VHDL
  • Prolog

Favorites

Programming icon

Programming

Travel icon

Travel

Soccer icon

Soccer

Ski icon

Ski / Snowboard

Sake icon

Japanese Sake

Wine icon

Wine

Diving icon

Diving

Swimming icon

Swimming

Fishing icon

Fishing

2022/06 PADI Open Water Diver (OWD) Certification Card
2022/06 ANSA Wine Examination Grade 3
2022/03 SSI Japanese Sake Examination Grade 3

Research / Education

Research

In the graduation thesis, I worked on accelerating an image processing filter called the bilateral filter using reconfigurable hardware (FPGA). Although image processing technology is applied in many fields such as medical diagnosis and self-driving, it is still difficult to process high-resolution images fast and small-scale. Therefore, I proposed its accelerator using parallelization and pipeline techniques, implemented on an FPGA, and verified that it was smaller and could process faster than the other existing approaches.

In the image processing fields, ML (Machine Learning) technology has been widely incorporated recently. Still, the technology requires more computation and execution time than the existing technologies. Therefore, I aim to create a helpful technology by building an acceleration mechanism specific to ML-based image and point-cloud processing technologies.

Presentations

2022/12 “FADEC: FPGA-based Acceleration of Video Depth Estimation by HW/SW Co-design” (Full Paper) @ The International Conference on Field Programmable Technology (FPT) (The top conference on FPGA)
Program, Paper (IEEE Xplore), Paper (arXiv), Papers With Code, GitHub, Slides (below), Movie
2022/10 “動画像を入力とした深度推定のHW/SW協調設計によるFPGAベースの高速化手法” @ System Architecture (ARC) (Information Processing Society of Japan (IPSJ))
Program and Abstract, Paper (Copyright ©2022 by IPSJ), Slides (below) (only in Japanese)
2022/09 “FPGAを用いたフルパイプラインによるバイラテラルフィルタの高速化手法” @ Forum on Information Technology (FIT) (Information Processing Society of Japan (IPSJ), etc.)
Program and Abstract
2022/03 “機械学習ベースの動画像処理における近似計算手法の検討” @ Technical Committee on Computer Systems (CPSY) (The Institute of Electronics, Information and Communication Engineers (IEICE))
Program and Abstract, Paper (Copyright ©2022 by IEICE), Slides (below) (only in Japanese)
2021/09 “An FPGA-Based Fully Pipelined Bilateral Grid for Real-Time Image Denoising” (Full Paper) @ The International Conference on Field-Programmable Logic and Applications (FPL) (The top conference on FPGA)
Program and Abstract, Paper (IEEE Xplore), Paper (arXiv), Papers With Code, GitHub, Slides (below), Movie
2021/06 “FPGAを用いたフルパイプラインによるバイラテラルフィルタの高速化手法” @ Technical Committee on Reconfigurable Systems (RECONF) (The Institute of Electronics, Information and Communication Engineers (IEICE))
“Best Presentation Award (young division)”
Program and Abstract, Paper (Copyright ©2021 by IEICE), Slides (below) (only in Japanese)

Education

2021/04 - present Department of Computer Science, Graduate School of Information Science and Technology, The University of Tokyo
2019/04 - 2021/03 Department of Information Science, School of Science, The University of Tokyo
2017/04 - 2019/03 Natural Sciences I, College of Arts and Sciences, The University of Tokyo
2014/04 - 2017/03 Seifu Nankai High School
2014/07 - 2014/08 Brisbane Grammar School (Australia) as an exchange student

Work

2021/04 - present Research Assistant at the University of Tokyo
Research on a multi-paradigm HLS (High-Level Synthesis) framework, which is easy to optimize the performance.
2021/10 - 2022/03 Teaching Assistant at the University of Tokyo
Assistance in the class of the Processor and Compiler Lab in the Department of Information Science.
2021/04 - 2021/07 Teaching Assistant at the University of Tokyo
Assistance in the class of the Hardware Lab in the Department of Information Science.
2020/01 - 2020/08 Long-term internship at A Co., Ltd.
Reverse Engineering of a product written in the C language. Development of an image processing AI using Python. Development of Websites and APIs using Django.
2019/08 Summer internship at M Ltd.
Proposal of a brand-new Web service and its development in a group using GitHub and AWS (see here). (Win the first prize.)
2019/02 - 2019/03 Long-term internship at BizWings (Thailand) Co., Ltd. in Thailand
Introduction of a business efficiency improving system.
2017/04 - 2019/03 Project Leader at AIESEC in the University of Tokyo
Operation of global internship programs as the incoming exchange department.
  • Overall support of internships in companies in Japan for foreign university students.
  • Proposal of the global internships to the companies in Japan.
  • Promotion of the global internships to the foreign students.
  • Support of the immigration procedures, including VISA applications.
  • Close communication with the internship participants to relieve anxiety, set the goals through the internship, and check the progress.
Co-creation with overseas AIESEC branches.
  • Participation in international conferences in Japan, in Taiwan, and in Sri Lanka.
  • Organization of pre-training for an internship by visiting a student in Macau.
Participation in the other projects.
  • Organization of an exchange meeting “Ikari-wo-ageyo” (only in Japanese) in Fujitsu Solution Square.
  • Plan and operation of welcoming events and external events.
  • Management of my project members.
2018/03 - 2018/05 Long-term internship at M Co., Ltd.
Blockchain survey writer.

Portfolio

FADEC icon

FADEC
Development of FADEC using NNgen, Vivado, Cython, and PYNQ. We published the paper “FADEC: FPGA-based Acceleration of Video Depth Estimation by HW/SW Co-design” @ FPT 2022.
Replacer icon

Replacer
Development of automatic string converter with multiple conditions using JavaScript. The demo and implementation details are available here.
Processor icon

4-stage pipelined RISC-V processor with privileged instructions
Development of 4-stage pipelined RISC-V processor with privileged instructions using System Verilog. Branch prediction using Two-level adaptive predictor and forwarding are also implemented to reduce stalls and accelerate the processor. Exception and interruption handlers are implemented by using CSR and privileged instructions (mret).
MLP icon

Multilayer Perceptron
Development of Multilayer Perceptron (MLP) for handwriting recognition from scratch using Python. 98.78 % accuracy in MNIST dataset.
Bilateral Grid icon

Fully Pipelined Bilateral Grid
Development of the Fully Pipelined Bilateral Grid on an FPGA using Vitis HLS, Vivado, and PYNQ. We published the paper “An FPGA-Based Fully Pipelined Bilateral Grid for Real-Time Image Denoising” @ FPL 2021.
Edge Layout Game icon

Edge Layout Game
Development of a user-friendly game considering UI (User Interface) in JavaScript and HTML / CSS. The Website is available here (only in Japanese).
Lay Tracing icon

CG Projects
Various implementations related to CG (Computer Graphics), including parametric curves, ray tracing, image filtering, and so on in JavaScript and HTML / CSS. The Website is available here.
RISC-V icon

RISC-V CPU
Group development of a CPU on an FPGA based on RISC-V. Development of FPU (Floating Point Unit) in System Verilog. Development of FPU simulation in C.
Raspberry Pi icon

Various lifehacks on a Raspberry Pi

Remote light controller using infrared LEDs. Voice operation using Julius. NAS (Network Attached Storage). Private Websites using Nginx and WordPress.
Tetris icon

Tetris
Development of a Tetris game in JavaScript and HTML / CSS.
Othello icon

Othello
Development of a strong Othello player in OCaml.

Slides

Achievements

2022/10 2nd grade Certified Skilled Professional of Financial Planning
2022/06 3rd grade Certified Skilled Professional of Financial Planning
2021/06 Best Presentation Award (young division) in Technical Committee on Reconfigurable Systems (RECONF)
2021/03 Education Network for Practical Information Technologies (enPiT)
2020/12 Applied Information Technology Engineer Examination
2020/02 TOEFL iBT Score: 98
2017/10 Driver's License
2017/08 TOEIC Score: 910
2016/08 Silver prize winner (only in Japanese) in Japan Physics Olympiad in 2016
2015/11 The EIKEN Test in Practical English Proficiency Grade Pre-1
2014/07 The Japan Kanji Aptitude Test Grade 2

Others

2021/05 - present Accountant in the Miyabi-kai (only in Japanese) (Alumuni group of the Ito Scholarship Foundation (only in Japanese)).
2021/04 - present Scholarship graduate student in the Ito Scholarship Foundation.
2022/10 Facilitator of “The JP-US-EU ICS Cybersecurity Week for the Indo-Pacific Region.”
2017/04 - 2021/03 Scholarship student in the Ito Scholarship Foundation.
2019/04 - 2020/03 Executive committee member to organize a two days workshop in the Ito Scholarship Foundation.
2019/09 Participation in “Scandinavian Blockchain Study Tour with Sota Watanabe” (only in Japanese) in Estonia and Finland.
2019/08 Instructor of science classes in “Japan-Australia Science Laboratory” (only in Japanese) in Australia.
2019/05 Keynote speech in “Symposium on Blockchain and Exchange Meetings” (only in Japanese). Slides are shown above (only in Japanese).